Conventionally, for the purpose of performing processing such as authentication and recognition with higher speed and low latency, a vision chip obtained by integrating an imaging portion and an image processing portion of an image sensor onto a chip has been under research.
For example, an imaging device has been known in which, in regard to a plurality of pixels two-dimensionally arranged in a matrix and having a photoelectric conversion function, one image processing circuit is disposed for one pixel, and image processing is performed in parallel. In this imaging device, image processing can be performed with higher speed and low latency. However, an image processing circuit generally occupies a larger area than a pixel size, which makes it difficult to make a pixel portion for photoelectric conversion large; thus, it has been difficult to obtain sufficient sensitivity characteristics. In addition, an area of one unit pixel including an image processing circuit and a pixel is large, which makes it difficult to increase the number of pixels.
Hence, Patent Literature 1 discloses large-scale integration (LSI) for pattern signal processing that employs a configuration in which one processor element is made to correspond to one column of sensors. Employing this configuration can, for example, reduce the number of image processing circuits necessary for pixels, and relax limitations on the pixel size and the number of pixels as described above.